To create a transistor, a polysilicon layer is deposited on top of a thin oxide layer. To form a resistor, a polysilicon layer is deposited on a field oxide layer. Both of these semiconductor devices may be made from the same polysilicon layer during the same process steps. The polysilicon layer, however, must be electrically isolated from the silicon substrate in order for these devices to operate. A buried contact may also be made from the same polysilicon layer as the gate electrode of a transistor and a resistor. The buried contact, however, requires an electrical connection between the polysilicon layer and the silicon substrate, generally where polysilicon and diffusion wires interconnect.
In the case of the buried contact, an opening is made in the oxide layer overlying the silicon substrate to expose a portion of the silicon. If a split polysilicon layer, or two polysilicon layers, are used to form the gate electrodes and resistors, the second polysilicon layer may be used to form the buried contacts.
The split polysilicon process is generally used in SRAM applications. After the formation of a field oxide layer in the case of a resistor or diode, and a gate oxide layer in the case of a gate electrode, the first amorphous or polysilicon layer is deposited. The buried contact openings to the silicon substrate are patterned, etched and doped, if necessary. The second amorphous or polysilicon layer is then deposited, patterned and etched to form the upper portion of the split polysilicon of the gate electrodes and resistors as well as the buried contact in the contact opening which connects directly to the silicon substrate.
During the gate electrode and resistor split polysilicon etch, both amorphous silicon or polysilicon layers are etched over the gate oxide and field oxide regions. With the buried contact, however, since the second amorphous or polysilicon layer forms the contact, only the second layer is etched during the etch step since the first layer has been removed previously. The thickness of the second polysilicon layer is obviously less than the thickness of the total split polysilicon stack forming the gate electrodes or resistors from the first and second polysilicon layers. In other words, the distance to etch the second polysilicon layer from the top of the resistors to the substrate is substantially less than the distance to etch the layer from the top of the gate electrode or resistor to the gate oxide or the field oxide.
At the location of the buried contact, there is no natural etch stop at the surface of the substrate such as oxide. In order to completely dry etch the gate electrodes and resistors, an overetching situation occurs while etching the buried contact due to the lesser height of polysilicon over the buried contact in relation to the height of the gates and resistors. This overetching condition results in an undesirable trenching of the silicon substrate. The depth of the trench is a function of the relative thicknesses of the first and second split polysilicon layers, as well as the surface topography. These factors dictate the amount of overetch required to clear the polysilicon away from the edge of the active areas around the gate and resistor devices.
In order to prevent the trenches from forming in the substrate during the dry etch process of the second split polysilicon layer, the present invention uses an etch stop layer disposed over the silicon substrate. This additional layer will act as an etch stop in any subsequent polysilicon etch to prevent trenching the silicon substrate around the buried contact area. This layer will also improve the contact resistance between the buried contact and the substrate.